公开(公告)号：US20030123454A1

公开(公告)日：2003-07-03

申请号：US10290766

申请日：2002-11-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Faraydon O. Karim ,  Ramesh Chandra ,  Bernd H. Stramm

IPC: H04L012/28

CPC classification number: H04L49/9031 ,  H04L49/90 ,  H04L49/901

Abstract: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.

Abstract translation: 存储用于由一个或多个网络处理器处理的分组的循环缓冲器使用空缓冲器地址寄存器来标识下一个接收到的分组应该被存储在哪里，下一个分组地址寄存器标识下一个待处理分组，以及一个分组处理地址寄存器 每个网络处理器识别由该网络处理器正在处理的分组。 缓冲区的n位地址通过软件从/到m位数据包处理地址寄存器映射或屏蔽，从而允许缓冲区大小完全可扩展。 由网络处理器支持的专用分组检索指令使用下一个分组地址寄存器检索新的分组进行处理，并将其复制到相关的分组处理地址寄存器中以用于随后的访问。 因此，缓冲区管理与网络处理器架构无关。