DAC with sub-DACs and related methods

    公开(公告)号:US09614542B2

    公开(公告)日:2017-04-04

    申请号:US14573083

    申请日:2014-12-17

    CPC classification number: H03M1/68

    Abstract: A DAC may include a decoder configured to receive a digital input signal, and first and second sub-DACs coupled in parallel to the decoder, each of the first and second sub-DACs having first and second LSB banks, and an MSB bank coupled between the first and second LSB banks. The decoder may be configured to selectively control the first and second LSB banks, and the MSB bank based upon the digital input signal. The DAC may include an output network coupled to the first and second sub-DACs and configured to generate an analog output signal related to the digital input signal.

Patent Agency Ranking