公开(公告)号：US20210286417A1

公开(公告)日：2021-09-16

申请号：US17194037

申请日：2021-03-05

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur BAL ,  Vikas CHELANI

IPC: G06F1/24 ,  G06F1/12

Abstract: An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.