公开(公告)号：US20040223364A1

公开(公告)日：2004-11-11

申请号：US10804562

申请日：2004-03-19

Applicant: STMICROELECTRONICS PVT. LTD.

Inventor： Rajeev Srivastavaan ,  Chiranjeev Grover

IPC: G11C015/00

CPC classification number: G11C15/00

Abstract: This invention provides, in an exemplary embodiment, a Content Addressable Memory (nullCAMnull) architecture providing improved speed by performing mutually exclusive operations in first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in the second state of the same clock cycles. The Content Addressable Memory (CAM) architecture comprises an array of CAM cells connected to a compare-data-write-driver and to a read/write block, for receiving the compare-data and for reading and/or writing data in the array of CAM cells respectively, outputs of the said CAM cell are coupled to a match block providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during first state and enabling read-or-write operations within the second state of the same clock cycle in the event of a match.

Abstract translation: 本发明在一个示例性实施例中提供了一种内容可寻址存储器（“CAM”）架构，其通过在时钟周期的第一状态下执行互斥操作并且依赖于至少一个先前的操作执行至少一个操作来提供改进的速度， 在相同时钟周期的第二个状态。 内容可寻址存储器（CAM）架构包括连接到比较数据写入驱动器和读/写块的CAM单元的阵列，用于接收比较数据并用于读取和/或写入数组中的数据 CAM单元，所述CAM单元的输出耦合到提供匹配输出信号线的匹配块，所述匹配输出信号线在搜索操作结束时识别匹配/不匹配;以及控制逻辑，用于在第一时间段期间实现搜索和地址解码操作 状态并且在匹配的情况下在相同时钟周期的第二状态内启用读或写操作。