公开(公告)号：US11740870B2

公开(公告)日：2023-08-29

申请号：US16833353

申请日：2020-03-27

申请人： STMICROELECTRONICS S.R.L. ,  STMicroelectronics International N.V.

发明人： Giuseppe Desoli ,  Thomas Boesch ,  Carmine Cappetta ,  Ugo Maria Iannuzzi

IPC分类号： G06F7/544 ,  G06N3/04

CPC分类号： G06F7/5443 ,  G06N3/04

摘要： A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.