公开(公告)号：US20240086152A1

公开(公告)日：2024-03-14

申请号：US18453158

申请日：2023-08-21

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Luca GANDOLFI ,  Ugo GAROZZO

IPC: G06F7/544

CPC classification number: G06F7/5443

Abstract: A device includes a multiplier, an accumulator and a floating point adder. The multiplier generates a product of a first factor having a sign bit and exponent bits and a second factor having a sign bit and exponent bits. The multiplier includes a sign multiplier and a subtractor. The sign multiplier generates a product of the sign bit of the first factor and the sign bit of the second factor. The subtractor subtracts the exponent bits of the first factor from the exponent bits of the second factor. The accumulator stores a current accumulation value. The floating-point adder is coupled to the multiplier and to the accumulator, and, in operation, the adder generates an updated accumulation value based a sum of the product and the current accumulation value, and stores the updated accumulation value in the accumulator. The first factor may be a weight of a neural network.