公开(公告)号：US20190057178A1

公开(公告)日：2019-02-21

申请号：US16160780

申请日：2018-10-15

Applicant: STMicroelectronics, Inc.

Inventor： Chetan BISHT ,  Harry SCRIVENER, III

IPC: G06F17/50 ,  H03K19/0175 ,  H03F3/195 ,  H03F3/60

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

公开(公告)号：US20160191058A1

公开(公告)日：2016-06-30

申请号：US14985887

申请日：2015-12-31

Applicant: STMicroelectronics, Inc.

Inventor： Chetan BISHT ,  Harry SCRIVENER, III

IPC: H03K19/0175 ,  H01L23/50 ,  H01L27/02 ,  H01L23/528

CPC classification number: H03K19/017509 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/50 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.