公开(公告)号：US20030214318A1

公开(公告)日：2003-11-20

申请号：US10146407

申请日：2002-05-14

Applicant: STMicroelectronics, Inc.

Inventor： Thomas David Zounes

IPC: H03K019/00

CPC classification number: G01R31/318541 ,  G01R31/318572

Abstract: A method and apparatus for disabling the scan output of flip-flops contained within an integrated circuit. Registers within the integrated circuit form a serial shift register chain when in the test mode of operation. The registers contain therein flip-flops, each of the flip-flops having at least one data input, a scan test input, a data output, and a scan output. The flip-flop is capable of storing either the signal appearing on the at least one data input or the signal appearing on the scan test input, based on the mode of operation of the flip-flop The flip-flop includes a circuit coupled between the data output and the scan output for selectively disabling the scan output from following the value of the data output. Consequently, the scan output is enabled to output the logic value stored in the flip-flop when the flip-flop is in the test mode of operation and is disabled from outputting the logic value stored in the flip-flop when the flip-flop is in the normal mode of operation. When the scan output is disabled from following the data output, the scan output is driven to a predetermined logic value.

Abstract translation: 一种用于禁止包含在集成电路内的触发器的扫描输出的方法和装置。 在测试运行模式下，集成电路内的寄存器形成串行移位寄存器链。 寄存器中包含触发器，每个触发器具有至少一个数据输入，扫描测试输入，数据输出和扫描输出。 触发器能够基于触发器的操作模式存储出现在至少一个数据输入端上的信号或出现在扫描测试输入端的信号。触发器包括耦合在触发器 数据输出和扫描输出，用于选择性地禁用扫描输出跟随数据输出的值。 因此，当触发器处于测试操作模式时，扫描输出能够输出存储在触发器中的逻辑值，并且当触发器为0时禁止输出存储在触发器中的逻辑值 在正常工作模式下。 当扫描输出从数据输出之后被禁止时，扫描输出被驱动到预定的逻辑值。