公开(公告)号：US20030020522A1

公开(公告)日：2003-01-30

申请号：US10099588

申请日：2002-03-13

Applicant: STMicroelectronics, Ltd.

Inventor： Andrew Dellow

IPC: H04L027/06 ,  H04L007/00

CPC classification number: H03K23/68 ,  H03K21/10 ,  H03K23/66

Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs adjacent such that are output is equal to the other delayed by one clock period. The outputs are passed to a multiplexer via further logic, the multiplexer selecting one of two inputs depending on whether a clock is high or low. Program logic is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively nulldeletingnull the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an nullevennull mark space ratio.

Abstract translation: 数字分频器具有单个循环移位寄存器，其加载可变长度的位序列，并且具有相邻的两个输出，使得输出等于另一个延迟一个时钟周期。 输出通过另外的逻辑被传送到多路复用器，多路复用器根据时钟是高还是低选择两个输入之一。 提供程序逻辑，使得通过检测0和1之间的位序列的变化，并且当检测到改变时选择性地“删除”前半个时钟周期，电路可配置为奇，偶或半整数除法。 这允许偶数，奇数或半整数时钟分频与“偶数”标记空间比。