公开(公告)号：US09813051B2

公开(公告)日：2017-11-07

申请号：US15052170

申请日：2016-02-24

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd

Inventor： Zhenghao Cui

IPC: H03K17/04 ,  H03K17/041 ,  H03K17/16

CPC classification number: H03K17/04106 ,  H03K17/165

Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.

公开(公告)号：US20170235321A1

公开(公告)日：2017-08-17

申请号：US15051406

申请日：2016-02-23

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd

Inventor： Zhenghao Cui

IPC: G05F1/575

CPC classification number: G05F1/575 ,  H02M3/156 ,  H02M2001/0032 ,  H02M2001/0045

Abstract: An electronic device disclosed herein includes a linear output stage configured to generate an output voltage to an output node as a function of an input voltage, and a buck output stage configured to generate the output voltage to the output node as a function of the input voltage. Control circuitry is configured to enable the linear output stage and disable the buck output stage if a current demanded by a load to maintain the output voltage at a desired level is less than a limit current, and enable the buck output stage and disable the linear output stage a delay period of time after enabling the buck output stage, if the current demanded by the load to maintain the output voltage at the desired level is greater than the limit current.

公开(公告)号：US09977445B2

公开(公告)日：2018-05-22

申请号：US15051406

申请日：2016-02-23

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd

Inventor： Zhenghao Cui

IPC: G05F1/565 ,  G05F1/575 ,  H02M1/00

CPC classification number: G05F1/575 ,  H02M3/156 ,  H02M2001/0032 ,  H02M2001/0045

Abstract: An electronic device disclosed herein includes a linear output stage configured to generate an output voltage to an output node as a function of an input voltage, and a buck output stage configured to generate the output voltage to the output node as a function of the input voltage. Control circuitry is configured to enable the linear output stage and disable the buck output stage if a current demanded by a load to maintain the output voltage at a desired level is less than a limit current, and enable the buck output stage and disable the linear output stage a delay period of time after enabling the buck output stage, if the current demanded by the load to maintain the output voltage at the desired level is greater than the limit current.

公开(公告)号：US20170237421A1

公开(公告)日：2017-08-17

申请号：US15052170

申请日：2016-02-24

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd

Inventor： Zhenghao Cui

IPC: H03K17/041 ,  H03K17/16

CPC classification number: H03K17/04106 ,  H03K17/165

Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.