METHOD FOR AUTHENTICATING AN ON-CHIP CIRCUIT AND ASSOCIATED SYSTEM ON-CHIP

    公开(公告)号:US20210117532A1

    公开(公告)日:2021-04-22

    申请号:US17071094

    申请日:2020-10-15

    Inventor: Olivier Giaume

    Abstract: An embodiment device comprises a first processing unit configured to process an initial data line and deliver a first processed data line, a first delay unit coupled to the output of the first processing unit and configured to deliver a delayed first processed data line delayed by a first delay, a second delay unit configured to deliver the delayed initial data line delayed by a second delay, a second processing unit coupled to the output of the second delay unit and configured to process the delayed initial data line and deliver a delayed second processed data line, and a comparison unit configured to compare the contents of the delayed first and second processed data lines and deliver a non-authentication signal if the contents are not identical, the first and second delays being equal to a variable value.

    Method for authenticating an on-chip circuit and associated system on-chip

    公开(公告)号:US11663314B2

    公开(公告)日:2023-05-30

    申请号:US17071094

    申请日:2020-10-15

    Inventor: Olivier Giaume

    CPC classification number: G06F21/44

    Abstract: An embodiment device comprises a first processing unit configured to process an initial data line and deliver a first processed data line, a first delay unit coupled to the output of the first processing unit and configured to deliver a delayed first processed data line delayed by a first delay, a second delay unit configured to deliver the delayed initial data line delayed by a second delay, a second processing unit coupled to the output of the second delay unit and configured to process the delayed initial data line and deliver a delayed second processed data line, and a comparison unit configured to compare the contents of the delayed first and second processed data lines and deliver a non-authentication signal if the contents are not identical, the first and second delays being equal to a variable value.

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