公开(公告)号：US20220179810A1

公开(公告)日：2022-06-09

申请号：US17539797

申请日：2021-12-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sandrine LENDRE ,  Herve CASSAGNES

IPC: G06F13/28

Abstract: A system on chip (SoC) includes a system clock device configured to generate at least one system clock signal, a first area with a central processing unit and a second area with a direct memory access (DMA) circuit, a peripheral coupled to the DMA circuit, and a memory containing peripheral configuration descriptor(s) executable by the DMA circuit. In a first mode of SoC operation, the system clock device delivers the system clock signal to all areas. In a second mode of SoC operation, the system clock device does not deliver the system clock signal to any area. In a third mode of SoC operation, the system clock device distributes the system clock signal to a part of the second area without delivering the system clock signal to the other areas and the DMA circuit configures the peripheral in response to the execution of the configuration descriptor(s).