-
公开(公告)号：US09389256B2
公开(公告)日：2016-07-12
申请号：US13717780
申请日：2012-12-18
发明人： Paolo Angelini , Giovanni Carlo Tripoli , Ernesto Lasalandra , Tommaso Ungaretti , Kien Beng Tan , Yannick Guedon , Dianbo Guo , Sze-Kwang Tan
CPC分类号： G01R27/2605 , G06F3/0418 , G06F3/044
摘要： Capacitance sensing circuits and methods are provided. The capacitance sensing circuit includes a capacitance-to-voltage converter configured to receive a signal from a capacitance to be sensed and to provide an output signal representative of the capacitance, an output chopper configured to convert the output signal of the capacitance-to-voltage converter to a sensed voltage representative of the capacitance to be sensed, an analog accumulator configured to accumulate sensed voltages during an accumulation period of NA sensing cycles and to provide an accumulated analog value, an amplifier configured to amplify the accumulated analog value, and an analog-to-digital converter configured to convert the amplified accumulated analog value to a digital value representative of the capacitance to be sensed. The analog accumulator may include a low pass filter having a frequency response to filter wideband noise.
-
公开(公告)号：US20140292375A1
公开(公告)日：2014-10-02
申请号：US13853870
申请日：2013-03-29
发明人： Paolo Angelini , Yannick Guedon , Ming Zi Zhu
IPC分类号： G11C27/02
CPC分类号： G06F3/044 , G03G7/00 , G06F3/0418 , G06G7/00
摘要： Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit.
摘要翻译： 用于完全或部分地从信号中去除噪声的累加器，包括消除蓄电池本身插入到信号中的噪声。 在一些实施例中，每当累加器对输入信号进行采样时，累加器可以在采样阶段和传送阶段中操作。 在一些这样的实施例中，累加器的累加电路的运算放大器可以在累积周期的某些或全部采样阶段期间自动归零。 在一些实施例中，在某些或所有采样相位期间运算放大器自动归零，其中累积电路可以包括保持电容器，其在自动归零过程期间保持由运算放大器输出的值 先前转移阶段。 在存储器中包括这种保持电容器可以降低运算放大器输出在自动归零过程之后上升的电压，这可以降低积累电路的带宽和噪声。
-
3.发明授权Configurable analog front-end for mutual capacitance sensing and self capacitance sensing 有权可配置的模拟前端，用于互电容感测和自电容感测公开(公告)号：US09523725B2
公开(公告)日：2016-12-20
申请号：US14322244
申请日：2014-07-02
发明人： Kien Beng Tan , Ernesto Lasalandra , Tommaso Ungaretti , Yannick Guedon , Dianbo Guo , Paolo Angelini , Giovanni Carlo Tripoli
CPC分类号： G01R27/2605 , G06F3/0416 , G06F3/044 , G06F2203/04104
摘要： Capacitance sensing circuits and methods are provided. A dual mode capacitance sensing circuit includes a capacitance-to-voltage converter having an amplifier and an integration capacitance coupled between an output and an inverting input of the amplifier, and a switching circuit responsive to mutual mode control signals for a controlling signal supplied from a capacitive touch matrix to the capacitive to voltage converter in a mutual capacitance sensing mode and responsive to self mode control signals for controlling signals supplied from the capacitive touch matrix to the capacitance-to-voltage converter in a self capacitance sensing mode, wherein the capacitance sensing circuit is configurable for operation in the mutual capacitance sensing mode or the self capacitance sensing mode.
摘要翻译： 提供电容感测电路和方法。 双模电容感测电路包括具有放大器和耦合在放大器的输出和反相输入端之间的积分电容器的电容 - 电压转换器，以及响应于从模拟信号提供的控制信号的相互模式控制信号的开关电路 电容式触摸矩阵到互电容感测模式中的电容到电压转换器，并且响应于用于在自电容感测模式中控制从电容式触摸矩阵提供给电容 - 电压转换器的信号的自模式控制信号，其中电容感测 电路可配置为在互电容感测模式或自身电容感测模式下工作。
-
4.发明申请公开(公告)号：US20140312919A1
公开(公告)日：2014-10-23
申请号：US14322244
申请日：2014-07-02
发明人： Kien Beng Tan , Ernesto Lasalandra , Tommaso Ungaretti , Yannick Guedon , Dianbo Guo , Paolo Angelini , Giovanni Carlo Tripoli
CPC分类号： G01R27/2605 , G06F3/0416 , G06F3/044 , G06F2203/04104
摘要： Capacitance sensing circuits and methods are provided. A dual mode capacitance sensing circuit includes a capacitance-to-voltage converter having an amplifier and an integration capacitance coupled between an output and an inverting input of the amplifier, and a switching circuit responsive to mutual mode control signals for a controlling signal supplied from a capacitive touch matrix to the capacitive to voltage converter in a mutual capacitance sensing mode and responsive to self mode control signals for controlling signals supplied from the capacitive touch matrix to the capacitance-to-voltage converter in a self capacitance sensing mode, wherein the capacitance sensing circuit is configurable for operation in the mutual capacitance sensing mode or the self capacitance sensing mode.
摘要翻译： 提供电容感测电路和方法。 双模电容感测电路包括具有放大器和耦合在放大器的输出和反相输入端之间的积分电容的电容 - 电压转换器，以及响应于从模拟信号提供的控制信号的相互模式控制信号的开关电路 电容式触摸矩阵到互电容感测模式中的电容到电压转换器，并且响应于用于在自电容感测模式中控制从电容式触摸矩阵提供给电容 - 电压转换器的信号的自模式控制信号，其中电容感测 电路可配置为在互电容感测模式或自身电容感测模式下工作。
-
公开(公告)号：US09235300B2
公开(公告)日：2016-01-12
申请号：US13853870
申请日：2013-03-29
发明人： Paolo Angelini , Yannick Guedon , Ming Zi Zhu
CPC分类号： G06F3/044 , G03G7/00 , G06F3/0418 , G06G7/00
摘要： Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit.
摘要翻译： 用于完全或部分地从信号中去除噪声的累加器，包括消除蓄电池本身插入到信号中的噪声。 在一些实施例中，每当累加器对输入信号进行采样时，累加器可以在采样阶段和传送阶段中操作。 在一些这样的实施例中，累加器的累加电路的运算放大器可以在累积周期的某些或全部采样阶段期间自动归零。 在一些实施例中，在某些或所有采样相位期间运算放大器自动归零，其中累积电路可以包括保持电容器，其在自动归零过程期间保持由运算放大器输出的值 先前转移阶段。 在存储器中包括这种保持电容器可以降低运算放大器输出在自动归零过程之后上升的电压，这可以降低积累电路的带宽和噪声。
-
6.发明授权Configurable analog front-end for mutual capacitance sensing and self capacitance sensing 有权可配置的模拟前端，用于互电容感测和自电容感测公开(公告)号：US08976151B2
公开(公告)日：2015-03-10
申请号：US13717766
申请日：2012-12-18
发明人： Kien Beng Tan , Ernesto Lasalandra , Tommaso Ungaretti , Yannick Guedon , Dianbo Guo , Paolo Angelini , Giovanni Carlo Tripoli
CPC分类号： G01R27/2605 , G06F3/0416 , G06F3/044 , G06F2203/04104
摘要： Capacitance sensing circuits and methods are provided. A dual mode capacitance sensing circuit includes a capacitance-to-voltage converter having an amplifier and an integration capacitance coupled between an output and an inverting input of the amplifier, and a dual mode switching circuit responsive to mutual mode control signals for a controlling signal supplied from a capacitive touch matrix to the capacitance-to-voltage converter in a mutual capacitance sensing mode and responsive to self mode control signals for controlling signals supplied from the capacitive touch matrix to the capacitance-to-voltage converter in a self capacitance sensing mode, wherein the capacitance sensing circuit is configurable for operation in the mutual capacitance sensing mode or the self capacitance sensing mode.
摘要翻译： 提供电容感测电路和方法。 双模电容感测电路包括具有放大器和耦合在放大器的输出和反相输入端之间的积分电容器的电容 - 电压转换器，以及响应于所提供的控制信号的相互模式控制信号的双模式切换电路 在互电容感测模式中从电容式触摸矩阵到电容 - 电压转换器，并且响应用于在自电容感测模式下控制从电容式触摸矩阵提供给电容 - 电压转换器的信号的自发模式控制信号， 其中电容感测电路可配置为在互电容感测模式或自电容感测模式下操作。
-
公开(公告)号：US12040628B2
公开(公告)日：2024-07-16
申请号：US17576052
申请日：2022-01-14
发明人： Yannick Guedon
CPC分类号： H02J50/12 , H02M1/0025 , H02M7/219
摘要： A bridge rectifier is controlled by control circuitry to act a “regtifier” which both regulates and rectifies without the use of a traditional voltage regulator. To accomplish this, the gate voltages of transistors of the bridge that are on during a given phase may be modulated to dissipate excess power. Gate voltages of transistors of the bridge that are off during the given phase may alternatively or additionally be modulated to dissipate excess power. The regtifier may act as two half-bridges that each power a different voltage converter, with those voltage converters powering a battery. The voltage converters may be switched capacitor voltage converters that switch synchronously with switching of the two half-bridges as they perform rectification.
-
公开(公告)号：US20240154460A1
公开(公告)日：2024-05-09
申请号：US18412718
申请日：2024-01-15
发明人： Yannick Guedon
CPC分类号： H02J50/10 , H02J7/0029 , H02J50/12 , H02J50/80
摘要： An over-voltage protection circuit and methods of operation are provided. In one embodiment, a method includes monitoring a voltage at an output of a rectifier, a voltage at an output of a voltage regulator, or a combination thereof. The method further includes determining the over-voltage condition based on the monitoring; and in response to determining the over-voltage condition, regulating the voltage at the output of the rectifier in accordance with a voltage difference between the voltage at the output of the rectifier and the voltage at the output of the voltage regulator.
-
公开(公告)号：US20210377084A1
公开(公告)日：2021-12-02
申请号：US17402108
申请日：2021-08-13
发明人： Yannick Guedon
摘要： A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample-and-hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal that have a same frequency, where the first control signal is configured to turn ON and OFF the first switch alternately, the second control signal is configured to turn ON and OFF the second switch alternately, and where the third control signal determines a sampling time of the first S&H circuit and has a first pre-determined delay from a first edge of the first control signal.
-
公开(公告)号：US20180101266A1
公开(公告)日：2018-04-12
申请号：US15840438
申请日：2017-12-13
发明人： Yannick Guedon , Sze-Kwang Tan , Dianbo Guo
CPC分类号： G06F3/044 , G06F3/0414 , G06F3/0416 , G06F2203/04103 , G06F2203/04108
摘要： A readout device for a capacitive sense matrix includes a computer readable storage medium configured to store capacitance data. The capacitance data represents capacitance values of the capacitive sense matrix. The readout device also includes a readout circuit configured to receive a signal from the capacitive sense matrix, the readout circuit being configured based upon the capacitance data. Also described are a readout method and a method of compensating for variations in capacitance.
-
-
-
-
-
-
-
-
-
搜索结果
50 条记录 (耗时 0.025 秒)
