公开(公告)号：US08527824B2

公开(公告)日：2013-09-03

申请号：US13739799

申请日：2013-01-11

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil Bahl ,  Akhil Garg

IPC: G01R31/3177 ,  G01R31/40

CPC classification number: G01R31/3177 ,  G01R31/318594

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.