公开(公告)号：US20240426908A1

公开(公告)日：2024-12-26

申请号：US18742474

申请日：2024-06-13

Applicant: STMicroelectronics International N.V.

Inventor： Andrea Floridia ,  Michelangelo Massimo Maria Grosso

IPC: G01R31/3185

Abstract: A scan-testable integrated circuit includes a logic circuit configured to receive test mode control signals, a signal interface configured to receive scan-in, scan enable and scan clock signals, and produce a scan-out signal, and a scan register including a plurality of scan cells coupled to the signal interface to receive the scan enable and scan clock signals. Additional scan cells are coupled to the signal interface, and configured to receive and propagate the scan-in signal when the scan enable signal is asserted. Data retention cells are coupled to respective ones of the additional scan cells and to the logic circuit, and configured to provide as output the values stored in the respective additional scan cells to produce the test mode control signals when the scan enable signal is de-asserted, and configured to prevent the test mode control signals from changing value when the scan enable signal is asserted.