公开(公告)号：US20250035703A1

公开(公告)日：2025-01-30

申请号：US18770967

申请日：2024-07-12

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur BAL ,  Aradhana KUMARI

IPC: G01R31/3185

Abstract: An integrated circuit is provided. For example, an integrated circuit comprises a functional data path and a scan-data path. At least a portion of the scan-data path is separate from the functional data path. The portion of the scan-data path which is separate from the functional data path comprises a combined gating/delay element for preventing a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode and for providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path.

公开(公告)号：US20230231546A1

公开(公告)日：2023-07-20

申请号：US18151332

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Aradhana KUMARI

IPC: H03K5/1252 ,  H03K5/135

CPC classification number: H03K5/1252 ,  H03K5/135

Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.

公开(公告)号：US20240372541A1

公开(公告)日：2024-11-07

申请号：US18775622

申请日：2024-07-17

Applicant: STMicroelectronics International N.V.

Inventor： Aradhana KUMARI

IPC: H03K5/1252 ,  H03K5/135

Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.