公开(公告)号：US20230403838A1

公开(公告)日：2023-12-14

申请号：US18454471

申请日：2023-08-23

Applicant: STMicroelectronics International N.V.

Inventor： Shafquat Jahan AHMED ,  Dhori Kedar JANARDAN

IPC: H10B10/00

CPC classification number: H10B10/12 ,  H10B10/18

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.