公开(公告)号：US08605530B2

公开(公告)日：2013-12-10

申请号：US13685363

申请日：2012-11-26

Applicant: STMicroelectronics International N.V.

Inventor： Sanjay Kumar Yadav ,  G Penaka Phani ,  Shailendra Sharad

IPC: G11C7/02

CPC classification number: G11C11/24 ,  G11C11/4091 ,  G11C11/4099

Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Abstract translation: 存储电路包括第一存储单元节点电容器，第一存储单元节点晶体管，具有第二存储单元节点电容器和第二存储单元节点晶体管的第二存储单元节点，以及预充电电路， 和第二存储单元节点分别为第一和第二电压电平。 该电路包括参考存储单元，该参考存储单元具有在其之间具有均衡晶体管的第一和第二参考单元晶体管，以及分别检测来自参考存储单元和第一或第二存储单元节点之间的参考位线之间的电位差的读出放大器。 参考单元晶体管和均衡晶体管基于分别输入到第一或第二参考单元晶体管的第一或第二参考信号，以预定电压和存储单元节点的第二电压均衡来执行存储单元节点的第一电压均衡。