公开(公告)号：US20240283736A1

公开(公告)日：2024-08-22

申请号：US18440216

申请日：2024-02-13

Applicant: STMicroelectronics International N.V.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo ,  Gianluca Di Carlo

IPC: H04L45/00 ,  H04L45/745 ,  H04L61/2546

CPC classification number: H04L45/566 ,  H04L45/745 ,  H04L61/2546

Abstract: A hardware network accelerator comprises a plurality of Ethernet communication interfaces, a plurality of memories, and a further memory. Each memory stores records comprising destination IP data identifying a destination IP address range. The further memory stores further records, wherein each record comprises next-hop data indicating a next-hop IP address, next-hop enable data, and network port data indicating an Ethernet communication interface. Each Ethernet communication interface is configured to obtain an IP packet, access in parallel the memories in order to read the records, select a record having a destination IP address range containing the destination IP address of the IP packet, read the further record associated with the selected record from the further memory, and select the indicated Ethernet communication interface. The selected Ethernet communication interface is configured to transmit an Ethernet frame comprising the IP packet based on the next-hop enable data and next-hop data.