公开(公告)号：US12095601B2

公开(公告)日：2024-09-17

申请号：US18064593

申请日：2022-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Andrea Mineo ,  Giovanni Amedeo Cirillo

IPC: H04L27/06

CPC classification number: H04L27/06

Abstract: According to an embodiment, a circuit for decoding a biphase mark coding (BMC) encoded signal is provided. The circuit includes a matched filter, a decoder circuit and a finite state machine (FSM) circuit. The matched filter is configured to generate a first response and a second response to the BMC encoded signal. The first response and second response operate respectively, at a half clock period and a full clock period of the BMC encoded signal. The detector circuit is coupled to an output of the matched filter. The detector circuit is configured to generate an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response. The FSM circuit is configured to decode the BMC encoded signal based on the output signal of the detector circuit.

公开(公告)号：US20240195665A1

公开(公告)日：2024-06-13

申请号：US18064593

申请日：2022-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Andrea Mineo ,  Giovanni Amedeo Cirillo

IPC: H04L27/06

CPC classification number: H04L27/06

Abstract: According to an embodiment, a circuit for decoding a biphase mark coding (BMC) encoded signal is provided. The circuit includes a matched filter, a decoder circuit and a finite state machine (FSM) circuit. The matched filter is configured to generate a first response and a second response to the BMC encoded signal. The first response and second response operate respectively, at a half clock period and a full clock period of the BMC encoded signal. The detector circuit is coupled to an output of the matched filter. The detector circuit is configured to generate an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response. The FSM circuit is configured to decode the BMC encoded signal based on the output signal of the detector circuit.