公开(公告)号：US20240332162A1

公开(公告)日：2024-10-03

申请号：US18616696

申请日：2024-03-26

Applicant: STMicroelectronics International N.V.

Inventor： William THIES ,  Gilles GASIOT ,  Andrea PAGANINI ,  Jerome DEROO ,  Matteo REPOSSI

IPC: H01L23/522 ,  H03H7/01

CPC classification number: H01L23/5223 ,  H01L23/5225 ,  H03H7/0115

Abstract: A device includes a substrate and an interconnection network on the substrate. The interconnection network includes at least a first level, at least a second level and a third level. The first level includes one or more capacitors. The third level includes a metallic shield. The second level is positioned between the first level and the substrate. The capacitors of the first level are entirely separated from the substrate by the shield. The second level is located between the first and third levels.