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公开(公告)号：US20250085737A1
公开(公告)日：2025-03-13
申请号：US18813588
申请日：2024-08-23
Applicant: STMicroelectronics International N.V.
Inventor： Patrick ARNOULD
IPC: G06F1/08
Abstract: Provided is a circuit for managing a first clock signal clocking a timer adapted to being controlled by a processor clocked by a second clock signal. When the processor is off, the first clock signal is equal to a third clock signal having a frequency lower than the frequency of the second clock signal. When the processor is on, the first clock signal is equal to a fourth signal having a rising edge at each rising edge of the second clock signal directly following a rising edge of the third clock signal.
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