公开(公告)号：US20250053478A1

公开(公告)日：2025-02-13

申请号：US18798040

申请日：2024-08-08

Applicant: STMicroelectronics International N.V.

Inventor： Raphael CLAUSS

IPC: G06F11/10

Abstract: A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.