公开(公告)号：US20240176384A1

公开(公告)日：2024-05-30

申请号：US17994654

申请日：2022-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Roberta PRIOLO

IPC: G06F1/08

CPC classification number: G06F1/08

Abstract: An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree. The delay circuit causes the state-overlap to exceed the tree propagation time.