公开(公告)号：US20140292385A1

公开(公告)日：2014-10-02

申请号：US13853247

申请日：2013-03-29

Applicant: STMicroelectronics International N.V.

Inventor： SWAPNIL BAHL ,  Shray Khullar

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G01R31/318575

Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

Abstract translation: 集成电路包括N个功能逻辑块，N个大于或等于2个，以及时钟交错测试电路。 当时钟交错测试电路处于移位模式时，为N个功能逻辑块中的相应的N个功能逻辑块生成N个交错的移位时钟信号。 N个交错移位时钟信号中的每一个具有等于外部测试时钟信号除以M的频率的频率，其中M大于或等于N.在移位模式期间，集成电路的峰值功率被减小，如 交错时钟信号的结果。