公开(公告)号：US20240319270A1

公开(公告)日：2024-09-26

申请号：US18612251

申请日：2024-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Shikhar MAKKAR

IPC: G01R31/3177

CPC classification number: G01R31/3177

Abstract: A system for performing scan testing on a device core uses a test access port (TAP). The TAP includes a test clock (TCK) pin, a test data in (TDI) pin, and a test mode select (TMS) pin, along with a test control register (TCR) associated with it. The TCR is used to set a scan mode signal, which configures the scan flip flops within the device core for scan testing and performs the scan testing on the device core. The TCR can also be reset to exit the scan testing, with the reset being triggered by a reset circuit receiving the deassertion of both a scan enable (SE) signal and a scan input (SI) signal during the capture-phase of scan testing.