CAPLESS ON CHIP VOLTAGE REGULATOR USING ADAPTIVE BULK BIAS
    1.
    发明申请
    CAPLESS ON CHIP VOLTAGE REGULATOR USING ADAPTIVE BULK BIAS 有权
    使用自适应大容量偏置的芯片电压调节器的封装

    公开(公告)号:US20150301540A1

    公开(公告)日:2015-10-22

    申请号:US14788682

    申请日:2015-06-30

    CPC classification number: G05F1/468 G05F1/56

    Abstract: An FDSOI integrated circuit die supplies on an output node a regulated output voltage based on a reference voltage. A pass transistor that passes a first current to the output node. A feedback loop regulates the output voltage by generating a second current based on the first current and applying a control signal to the pass transistor based on the second current. A loop current adaptor adapts a ratio of the first and second currents by adjusting a back gate bias voltage applied to a back gate of loop transistor of the feedback loop.

    Abstract translation: FDSOI集成电路管芯在输出节点上提供基于参考电压的稳压输出电压。 将第一电流传递到输出节点的传输晶体管。 反馈回路基于第一电流产生第二电流并基于第二电流向控制晶体管施加控制信号来调节输出电压。 环路电流适配器通过调整施加到反馈回路的环形晶体管的背栅的背栅偏置电压来适配第一和第二电流的比率。

Patent Agency Ranking