公开(公告)号：US20020120908A1

公开(公告)日：2002-08-29

申请号：US10061949

申请日：2002-01-31

Applicant: STMicroelectronics S.r.I.

Inventor： Amedeo La Scala

IPC: G06F017/50

CPC classification number: G01R31/318505 ,  G01R31/318558

Abstract: Management of Test Access Port functions of a plurality of components arranged on a single chip by selectively driving the TAP function of each of the components with respective clocks, whilst the further signals for driving the TAP function are used in a shared mode among the various components. Preferably, associated with the aforesaid clocks is a pull-down function for selectively blanking the respective clocks in conditions of non-use. In a preferred way, the aforesaid dedicated clocks are generated on board the chip.

Abstract translation: 管理测试访问通过选择性地以相应的时钟驱动每个组件的TAP功能，同时在各种组件中以共享模式使用用于驱动TAP功能的另外的信号，在单个芯片上布置的多个组件的端口功能 。 优选地，与上述时钟相关联的是用于在不使用的条件下选择性地消隐各个时钟的下拉功能。 在优选的方式中，上述专用时钟在芯片上产生。