公开(公告)号：US20040225869A1

公开(公告)日：2004-11-11

申请号：US10776024

申请日：2004-02-10

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Pagni ,  Fabrizio Lucini ,  Danilo Pietro Pau ,  Antonio Maria Borneo ,  Vittorio Zaccaria

IPC: G06F009/44

CPC classification number: G06F9/30174 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3879

Abstract: A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to the ARM instructions and a second set of registers corresponding to the instructions that can be executed on the LX processor. Each register of the first set is mapped in a corresponding register of the second set designed to emulate the behavior of the first register, obtaining a unique independent translation of the first set into the second set. The translation is performed by a translation device external to the LX core without altering the core, and the translation operating without accessing resources of the core, by the translating device intercepting accesses of the core to the storage area reserved to the ARM instructions.

Abstract translation: 用于将第一集合的ARM指令转换为用于在包括核的LX处理器上执行的第二集合的指令的过程提供对应于ARM指令的第一组寄存器和对应于可执行的指令的第二组寄存器 在LX处理器上。 将第一组的每个寄存器映射到第二组的对应寄存器中，该寄存器被设计为模拟第一寄存器的行为，从而获得第一集合到第二集合中的唯一的独立转换。 翻译由LX核心外部的翻译设备执行，而不改变核心，并且通过翻译设备将核心的访问拦截到保留给ARM指令的存储区域，而不会访问核心的资源。

公开(公告)号：US20040059894A1

公开(公告)日：2004-03-25

申请号：US10612825

申请日：2003-07-01

Applicant: STMicroelectronics S.r.I.

Inventor： Fabrizio Simone Rovati ,  Antonio Maria Borneo ,  Danilo Pietro Pau

IPC: G06F015/00 ,  G06F015/76

CPC classification number: G06F9/3879 ,  G06F9/3853 ,  G06F9/3877

Abstract: The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order. There is defined a sequence of execution of the instructions in successive operating cycles of the processor system, assigning each sub-bundle to an operating cycle, thus preventing simultaneous assignment to the same operating cycle of two sub-bundles belonging to the first set of two successive bundles. The instructions of the sequence may be executed by the various processors of the system in conditions of binary compatibility.

Abstract translation: 将要执行的程序通过将其转换为处理器系统的指令集体系结构的本机指令而进行编译，将按程序的翻译导出的指令按照连续的捆的顺序进行组织， 由处理器系统并行执行。 所述指令束被排列到相应的子束中，所述子束标识第一组指令，其必须在属于所述命令的下一束的指令之前执行，以及可以执行的第二组指令 在属于所述顺序的所述后续束的指令之前和之后。 在处理器系统的连续操作周期中定义了执行指令的顺序，将每个子束分配到操作周期，从而防止同时分配属于第一组二的两个子束的相同操作周期 连续捆绑 序列的指令可以由系统的各种处理器在二进制兼容性的条件下执行。