公开(公告)号：US20230087074A1

公开(公告)日：2023-03-23

申请号：US17940753

申请日：2022-09-08

Applicant: STMicroelectronics S.r.I.

Inventor： Gianbattista Lo Giudice ,  Antonino Conte

IPC: G11C16/24 ,  G11C16/26

Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.

公开(公告)号：US12205651B2

公开(公告)日：2025-01-21

申请号：US17940753

申请日：2022-09-08

Applicant: STMicroelectronics S.r.I.

Inventor： Gianbattista Lo Giudice ,  Antonino Conte

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/26

Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.