公开(公告)号：US20030068037A1

公开(公告)日：2003-04-10

申请号：US09974176

申请日：2001-10-10

Applicant: STMicroelectronics S.r.I.

Inventor： Guido Bertoni ,  Luca Breveglieri ,  Pasqualina Fragneto

IPC: H04L009/00

CPC classification number: G06F7/724

Abstract: A circuit for computing the inner of scalar product of two vectors in a finite Galois field defined by a generator polynomial, wherein each vector includes at least two elements belonging to said finite field, comprises one or more look-up tables storing digital words indicative of said possible combinations and said possible reductions. The digital words in question are defined as a function of the second elements of said vectors and the generator polynomial of the field. The input register(s) and the look-up table(s) are configured to co-operate in a plurality of subsequent steps to generate at each step a partial product result identified by at least one of digital word addressed in a corresponding look-up table as a function of the digital signals stored in the input register(s). The circuit also includes an accumulator unit for adding up the partial results generated at each step to give a final product result deriving from accumulation of said partial results.

Abstract translation: 一种用于计算由生成多项式定义的有限伽罗瓦域中的两个向量的标量积的内部的电路，其中每个向量包括属于所述有限域的至少两个元素，包括一个或多个查找表，其存储指示 说可能的组合和所述可能的减少。 所讨论的数字词被定义为所述向量的第二元素和场的生成多项式的函数。 输入寄存器和查找表被配置为在多个后续步骤中协作以在每个步骤处生成由相应查找表中寻址的数字字中的至少一个标识的部分乘积结果， 作为存储在输入寄存器中的数字信号的函数。 该电路还包括用于将在每个步骤产生的部分结果相加以产生从所述部分结果的积累得到的最终产品结果的累加器单元。