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公开(公告)号：US10965254B2
公开(公告)日：2021-03-30
申请号：US16392009
申请日：2019-04-23
Applicant: STMicroelectronics S.r.l.
Inventor： Mattia Fausto Moretti , Paolo Pulici , Alessio Facen
Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
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公开(公告)号：US11855588B2
公开(公告)日：2023-12-26
申请号：US17581334
申请日：2022-01-21
Applicant: STMicroelectronics S.r.l.
Inventor： Edoardo Marino , Alessio Vallese , Alessio Facen , Enrico Mammei , Paolo Pulici
CPC classification number: H03F1/3211 , H03F3/45179 , H03F3/45479 , H03F3/4508 , H03F3/45085
Abstract: In an embodiment, an electronic circuit includes: an input differential pair including first and second transistors; a first pair of transistors in emitter-follower configuration including third and fourth transistors, and an output differential pair including fifth and sixth transistors. The third transistor has a control terminal coupled to the first transistor, and a current path coupled to a first output terminal. The fourth transistor has a control terminal coupled to the second transistor, and a current path coupled to a second output terminal. The fifth transistor has a control terminal coupled to the first transistor, and a first current path terminal coupled to the first output terminal. The sixth transistor has a control terminal coupled to the second transistor, and a first current path terminal coupled to the second output terminal. First and second termination resistors are coupled between the first pair of transistors and the output differential pair.
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Patent Agency Ranking
公开(公告)号：US20230238921A1
公开(公告)日：2023-07-27
申请号：US17581334
申请日：2022-01-21
Applicant: STMicroelectronics S.r.l
Inventor： Edoardo Marino , Alessio Vallese , Alessio Facen , Enrico Mammei , Paolo Pulici
CPC classification number: H03F1/3211 , H03F3/45179 , H03F3/45479 , H03F3/4508
Abstract: In an embodiment, an electronic circuit includes: an input differential pair including first and second transistors; a first pair of transistors in emitter-follower configuration including third and fourth transistors, and an output differential pair including fifth and sixth transistors. The third transistor has a control terminal coupled to the first transistor, and a current path coupled to a first output terminal. The fourth transistor has a control terminal coupled to the second transistor, and a current path coupled to a second output terminal. The fifth transistor has a control terminal coupled to the first transistor, and a first current path terminal coupled to the first output terminal. The sixth transistor has a control terminal coupled to the second transistor, and a first current path terminal coupled to the second output terminal. First and second termination resistors are coupled between the first pair of transistors and the output differential pair.
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公开(公告)号：US20230009311A1
公开(公告)日：2023-01-12
申请号：US17952574
申请日：2022-09-26
Applicant: STMicroelectronics S.r.l.
Inventor： Mattia Fausto Moretti , Paolo Pulici , Alessio Facen
Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
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公开(公告)号：US11894810B2
公开(公告)日：2024-02-06
申请号：US17952574
申请日：2022-09-26
Applicant: STMicroelectronics S.r.l.
Inventor： Mattia Fausto Moretti , Paolo Pulici , Alessio Facen
CPC classification number: H03F1/26 , H03F3/45192
Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
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公开(公告)号：US20230314117A1
公开(公告)日：2023-10-05
申请号：US18191689
申请日：2023-03-28
Applicant: STMicroelectronics S.r.l.
Inventor： Dario Livornesi , Mattia Fausto Moretti , Paolo Pulici , Alessio Emanuele Vergani , Alessio Facen , Michele Bartolini , Roberto Faravelli , Francesco Piscitelli
Abstract: According to an embodiment, a circuit includes a core and low-frequency recovery circuits. The core circuit is configured to bias a resistive sensor used to measure a fly height of a hard disk drive. The core circuit is additionally configured to amplify a high-frequency component of a sensing signal of the resistive sensor, the sensing signal indicating the fly height. The low-frequency recovery circuit is configured to amplify the sensing signal's low-frequency component.
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公开(公告)号：US11489496B2
公开(公告)日：2022-11-01
申请号：US17172676
申请日：2021-02-10
Applicant: STMicroelectronics S.r.l.
Inventor： Mattia Fausto Moretti , Paolo Pulici , Alessio Facen
Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
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