公开(公告)号：US20160072448A1

公开(公告)日：2016-03-10

申请号：US14746124

申请日：2015-06-22

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Francesco CARRARA ,  Felice Alberto TORRISI ,  Francesco CLERICI

IPC: H03F1/08 ,  H03F3/45 ,  H03F1/02

CPC classification number: H03F1/086 ,  H03F1/0205 ,  H03F1/083 ,  H03F3/45085 ,  H03F3/45179 ,  H03F3/45502 ,  H03F3/45511 ,  H03F2200/456 ,  H03F2203/45008 ,  H03F2203/45116 ,  H03F2203/45288 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45431

Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.

Abstract translation: 共模反馈电路包括具有差分输入端的跨导体输入级，以及耦合到具有差分输出端的跨导体输入级的频率补偿增益级。 共模反馈电路还包括反馈回路，其具有比较器，该比较器被配置为通过与参考相比较来产生用于跨导体输入级的反馈误差信号，该共模检测信号表示在差分输出处感测到的共模电压电平 终端。 此外，共模反馈环路包括用于将在所述差分输出端子处感测的共模电压电平转换为耦合到比较器的电流信号的转换器。

公开(公告)号：US20220397924A1

公开(公告)日：2022-12-15

申请号：US17836417

申请日：2022-06-09

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele MANGANO ,  Francesco CLERICI ,  Pasquale BUTTA'

IPC: G05F1/56 ,  G05F1/46

Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.

公开(公告)号：US20220397923A1

公开(公告)日：2022-12-15

申请号：US17836524

申请日：2022-06-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Daniele MANGANO ,  Andrei TUDOSE ,  Francesco CLERICI ,  Pasquale BUTTA'

IPC: G05F1/46 ,  G06F1/3296

Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.