公开(公告)号：US20230043943A1

公开(公告)日：2023-02-09

申请号：US17870173

申请日：2022-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola ERRICO ,  Valerio BENDOTTI ,  Luca FINAZZI ,  Gaudenzia BAGNATI

IPC: H03K17/16 ,  H02M3/158

Abstract: A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.