公开(公告)号：US20240088875A1

公开(公告)日：2024-03-14

申请号：US18451272

申请日：2023-08-17

Applicant: STMicroelectronics S.r.l.

Inventor： Pietro Antonino Coppa ,  Gianbattista Lo Giudice ,  Enrico Castaldo ,  Antonino Conte

IPC: H03K3/03 ,  H03K3/011

CPC classification number: H03K3/0315 ,  H03K3/011

Abstract: An electronic system is configured to generate a sequential logic signal. The electronic system includes a first ring oscillator including a first plurality of cascaded inverter stages. A combinational logic circuit is configured to generate the sequential logic signal by combining signals at the output terminals of at least two of the inverter stages of the first ring oscillator. The electronic system further includes a second ring oscillator including a second plurality of cascaded inverter stages. A bias current source is configured to supply the inverter stages of the second ring oscillator with a bias current, and a first voltage is generated at the inverter stages of the second ring oscillator. A voltage follower is configured to supply the inverter stages of the first ring oscillator with a second voltage corresponding to the first voltage generated at the inverter stages of the second ring oscillator.