公开(公告)号：US20040135234A1

公开(公告)日：2004-07-15

申请号：US10701165

申请日：2003-11-04

Applicant: STMicroelectronics SA

Inventor： Pierre Morin ,  Jorge Luis Regolini

IPC: H01L023/58

CPC classification number: H01L29/7842 ,  H01L21/823814 ,  H01L21/823828 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between the MOS transistors and the dielectric layer. The etch-stop layer includes a first layer of material having a first residual stress level and covers some of the MOS transistors, and a second layer of material having a second residual stress level and covers all of the MOS transistors. The respective thickness of the first and second layers of material, and the first and second residual stress levels associated therewith are selected to obtain variations in operating parameters of the MOS transistors.

Abstract translation: 半导体器件包括衬底，衬底中的MOS晶体管和MOS晶体管上的介电层。 通过介电层形成接触孔以提供与MOS晶体管的电连接。 蚀刻停止层位于MOS晶体管和电介质层之间。 蚀刻停止层包括具有第一残余应力水平并且覆盖一些MOS晶体管的第一材料层和具有第二残余应力水平并覆盖所有MOS晶体管的第二材料层。 选择第一和第二层材料的相应厚度以及与其相关联的第一和第二残余应力水平以获得MOS晶体管的操作参数的变化。