公开(公告)号：US20040062108A1

公开(公告)日：2004-04-01

申请号：US10383153

申请日：2003-03-06

Applicant: STMicroelectronics SA

Inventor： Cyrille Dray ,  Phillipe Gendrier ,  Richard Fournel

IPC: G11C007/00

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: The semiconductor memory device includes a non-volatile programmable and electrically erasable memory cell with a single layer of gate material and a floating gate transistor and a control gate, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of gate material in which the floating gate is made extends integrally above the active area without overlapping part of the isolation region, and the transistor is electrically isolated from the control gate by PN junctions that will be inverse polarized.

Abstract translation: 半导体存储器件包括具有单层栅极材料的非易失性可编程和电可擦除存储单元，以及浮置栅极晶体管和控制栅极，该有源半导体区域形成在衬底的区域中并由隔离区限定 。 其中制造浮栅的栅极材料层在有源区域上整体地延伸而不重叠隔离区的一部分，并且晶体管通过将被反极化的PN结与控制栅极电隔离。