公开(公告)号：US20200212927A1

公开(公告)日：2020-07-02

申请号：US16709391

申请日：2019-12-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Stephane LE TUAL ,  Jean-Pierre BLANC ,  David DUPERRAY

IPC: H03M1/68 ,  H03M1/06

Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.