公开(公告)号：US11264977B1

公开(公告)日：2022-03-01

申请号：US17184409

申请日：2021-02-24

Applicant: SYNAPTICS INCORPORATED

Inventor： Jae Won Choi ,  Dan Shen ,  Balakishan Challa ,  Lorenzo Crespi ,  Ketan Patel

IPC: H03K5/1536 ,  G01R19/175 ,  H02M1/08 ,  H02M1/00

Abstract: Embodiments described herein provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter. The ZCD includes a ZCD integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate a zero-crossing detect signal based, at least in part, on the received switch voltage and output voltage, where the zero-crossing detect signal is configured to indicate an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.

公开(公告)号：US12026009B2

公开(公告)日：2024-07-02

申请号：US18061936

申请日：2022-12-05

Applicant: Synaptics Incorporated

Inventor： Chandra Shekar Reddy Ayya ,  Jae Won Choi

IPC: G06F1/08 ,  G06F1/14

CPC classification number: G06F1/14 ,  G06F1/08

Abstract: Quadrature clock generation circuits and techniques are disclosed. An example quadrature clock generator includes an in-phase (I) clock generation circuit to generate an I clock signal based on a reference clock signal, the I clock signal and the reference clock signal each having a first frequency, a quadrature phase (Q) clock generation circuit to generate a Q clock signal based on the reference clock signal, a rise time control signal, and a fall time control signal, the Q clock signal having the first frequency, and a control circuit to generate the rise time control signal and the fall time control signal based on the I clock signal and the Q clock signal.

公开(公告)号：US11594964B2

公开(公告)日：2023-02-28

申请号：US17109087

申请日：2020-12-01

Applicant: SYNAPTICS INCORPORATED

Inventor： Jae Won Choi ,  Dan Shen ,  Balakishan Challa ,  Lorenzo Crespi ,  Ketankumar B. Patel

IPC: H02M3/157 ,  H02M1/00

Abstract: A circuit includes a controller circuit configured to receive an output voltage of a converter and adjust a switching frequency of the converter in response to a status of an output load and an output load sensing circuit configured to determine the status of the output load and provide the peak current to the controller circuit. The output load sensing circuit may include a first timer configured to provide a delayed first signal to a peak current control in response to the output load being a heavy load. A second timer may be configured to provide a delayed second signal to the peak current control in response to the output load being a light load. The peak current control may be configured to adjust a peak current based on the received first signal and the second signal and configured to provide the peak current to the controller circuit.