利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

1 条记录 (耗时 0.016 秒)

    METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT IN WHICH FAULT DETECTION CAN BE EFFECTED THROUGH SCAN-IN AND SCAN-OUT
    1.
    发明申请
    METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT IN WHICH FAULT DETECTION CAN BE EFFECTED THROUGH SCAN-IN AND SCAN-OUT 审中-公开
    设计通过扫描和扫描可以影响故障检测的半导体集成电路的方法

    公开(公告)号：US20090106721A1

    公开(公告)日：2009-04-23

    申请号：US12334988

    申请日：2008-12-15

    申请人： Sadami TAKEOKA ,  Takahiro ICHINOMIYA ,  Akira MOTOHARA

    发明人： Sadami TAKEOKA ,  Takahiro ICHINOMIYA ,  Akira MOTOHARA

    IPC分类号： G06F17/50

    CPC分类号： G01R31/318586

    摘要： A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

    摘要翻译： 一种设计半导体集成电路的方法包括以下步骤：选择要作为扫描链连接的一对扫描寄存器，并计算硬件上从前级扫描寄存器的每个输出端到扫描数据输入端的扫描数据输入端 后级扫描寄存器。 该方法还包括以下步骤：基于上述计算，在具有最小直线距离的前级选择扫描寄存器的输出端; 确定将所选输出端与后级扫描寄存器的扫描数据输入端连接; 以及通过使用在前一步骤中确定的输出端子连接每对扫描寄存器来形成扫描链。