公开(公告)号：US20230380239A1

公开(公告)日：2023-11-23

申请号：US18318066

申请日：2023-05-16

Applicant: Samsung Display Co., Ltd.

Inventor： Sanghyung Lim ,  Soonmi Choi ,  Ran Kim ,  Younggil Park ,  Dongyeon Cho

IPC: H10K59/38 ,  H10K59/80 ,  H10K59/131

CPC classification number: H10K59/38 ,  H10K59/879 ,  H10K59/131

Abstract: A display apparatus includes first to third light-emitting elements disposed on a substrate, a first-color light output layer, a second-color quantum dot layer, and a third-color quantum dot layer, which are disposed on the first to third light-emitting elements, respectively, a first capping layer disposed on the first-color light output layer, the second-color quantum dot layer, and the third-color quantum dot layer to correspond to the first to third light-emitting elements, a low-refractive-index layer disposed on the first capping layer, a first barrier layer between the first capping layer and the low-refractive-index layer, a first-color color filter layer disposed on the low-refractive-index layer to correspond to the first light-emitting element, a second-color color filter layer disposed on the low-refractive-index layer to correspond to the second light-emitting element, and a third-color color filter layer disposed on the low-refractive-index layer to correspond to the third light-emitting element.

公开(公告)号：US20230413617A1

公开(公告)日：2023-12-21

申请号：US18170204

申请日：2023-02-16

Applicant: Samsung Display Co., LTD.

Inventor： Dongyeon Cho ,  Kihyun Kim ,  Younggil Park

IPC: H10K59/124 ,  H10K59/12 ,  H10K59/121 ,  H10K59/131

CPC classification number: H10K59/124 ,  H10K59/1201 ,  H10K59/1213 ,  H10K59/1216 ,  H10K59/131

Abstract: A display apparatus includes a thin film transistor including a semiconductor pattern including an oxide semiconductor and a gate electrode overlapping the semiconductor pattern, a first interlayer insulating layer on the semiconductor pattern and the gate electrode, and a connection electrode on the first interlayer insulating layer and contacting the semiconductor pattern through a contact hole penetrating the first interlayer insulating layer, wherein the connection electrode entirely covers the gate electrode in a plan view, and an end portion of the gate electrode is spaced apart from the contact hole by a first distance.