DISPLAY APPARATUS
    2.
    发明公开
    DISPLAY APPARATUS 审中-公开

    公开(公告)号:US20230422559A1

    公开(公告)日:2023-12-28

    申请号:US18320069

    申请日:2023-05-18

    CPC classification number: H10K59/122 H10K59/1315

    Abstract: A display apparatus includes: a first pixel electrode and a second pixel electrode spaced apart from each other on a substrate; a pixel defining layer having a first opening exposing a central portion of the first pixel electrode and a second opening exposing a central portion of the second pixel electrode; a separator above the pixel defining layer and, in a plan view, between the first opening and the second opening; a connection electrode between the pixel defining layer and the separator; a first intermediate layer on the first pixel electrode; a second intermediate layer on the second pixel electrode and spaced apart from the first intermediate layer; a first counter electrode on the first intermediate layer and electrically connected to the connection electrode; and a second counter electrode on the second intermediate layer, spaced apart from the first counter electrode, and electrically connected to the connection electrode.

    DISPLAY APPARATUS
    3.
    发明公开
    DISPLAY APPARATUS 审中-公开

    公开(公告)号:US20240324294A1

    公开(公告)日:2024-09-26

    申请号:US18520556

    申请日:2023-11-28

    Abstract: A display apparatus includes a substrate including a display area and a peripheral area, a first semiconductor layer including a driving semiconductor pattern, a first conductive layer disposed on the first semiconductor layer, and including a first capacitor electrode and a second capacitor electrode, a second conductive layer disposed on the first conductive layer, and including a third capacitor electrode overlapping the first capacitor electrode and the second capacitor electrode, a second semiconductor layer disposed on the second conductive layer, and including a first semiconductor pattern overlapping the third capacitor electrode, a third conductive layer disposed on the second semiconductor layer, and including a first electrode pattern overlapping the first semiconductor pattern and the third capacitor electrode, and a fourth conductive layer disposed on the third conductive layer, and including a connection electrode electrically connected to the first semiconductor pattern and the third capacitor electrode.

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