公开(公告)号：US20220181420A1

公开(公告)日：2022-06-09

申请号：US17471849

申请日：2021-09-10

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM ,  MEEJAE KANG ,  THANH TIEN NGUYEN ,  HYENA KWAK ,  JAEHWAN CHU

IPC: H01L27/32

Abstract: A display device may include a substrate, a first transistor disposed on the substrate and including a first gate electrode, a first conductive pattern disposed on the first gate electrode such that the first conductive pattern and the first gate electrode constitute a first capacitor, a second conductive pattern disposed on the first capacitor, a third conductive pattern disposed on the second conductive pattern such that the third conductive pattern and the second conductive pattern constitute a second capacitor, and a light emitting structure disposed on the second capacitor.

公开(公告)号：US20210367209A1

公开(公告)日：2021-11-25

申请号：US17228586

申请日：2021-04-12

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM ,  HYENA KWAK ,  TAEWOOK KANG ,  JIYEONG SHIN ,  JAESEOB LEE

IPC: H01L51/52

Abstract: A display device includes: a base substrate including a first polymeric film; an active pattern on the base substrate and including a first channel region; and a first gate electrode overlapping the first channel region, wherein the first polymeric film has a first thickness in a first area overlapping the first channel region and a second thickness, which is smaller than the first thickness, in a second area different from the first area.

公开(公告)号：US20210335953A1

公开(公告)日：2021-10-28

申请号：US17079765

申请日：2020-10-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： KEUNWOO KIM ,  HYENA KWAK ,  SANGSUB KIM ,  HANBIT KIM

IPC: H01L27/32 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3233

Abstract: A pixel includes: a driving transistor including a semiconductor layer and a gate electrode; and a compensation transistor connected to the gate electrode and the semiconductor layer of the driving transistor, wherein the first thin-film transistor includes: a first sub-transistor including a first gate electrode receiving a first scan signal having a first voltage level during a period; and a second sub-transistor connected to the first sub-transistor in parallel and comprising a second gate electrode receiving a second scan signal having a second voltage level that is an inverted level of the first voltage level during the same period.