Abstract:
A display apparatus includes gate lines extending in a first direction, data lines extending in a second direction crossing the first direction, and pixels connected to the gate lines and the data lines. The pixels include pixels arranged in a k-th column between a k-th data line and a (k+1)th data line. The pixels arranged in the k-th column are arranged in a plurality of groups, and each of the groups includes 2i first pixels connected to the k-th data line and 2i second pixels connected to the (k+1)th data line. Successive ones of the pixels in each group are connected to the k-th data line and the (k+1)th data line in alternating manner.
Abstract:
Provided is a display apparatus including a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a plurality of pixels and a plurality of sub-pixels. Two pixels among the pixels include five sub-pixels and temporally share a third sub-pixel among the five sub-pixels. The timing controller includes a filter that is set based on a region having the same area as four sub-pixels. The timing controller generates RGBW data having red, green, blue, and white data based on input data, and applies the filter to the RGBW data to generate output data corresponding to each of the sub-pixels.
Abstract:
A display apparatus includes a display panel including a first pixel configured to include first and second sub-pixels and a second pixel configured to include third and fourth sub-pixels. A timing controller generates pixel data including first and second pixel data respectively corresponding to the first and second pixels and representable in a second matrix space, from pixel signals including first and second pixel signals representable in a first matrix space to respectively correspond to the first and second pixels. The timing controller generates the second pixel data on the basis of the first pixel signal adjacent to the second pixel signal which correspond to each second pixel data in the column direction in the first matrix space.
Abstract:
An image processing circuit includes a mapper configured to convert an image signal into an intermediate data signal, and a renderer configured to convert the intermediate data signal into a data signal, wherein the renderer includes a memory configured to store the intermediate data signal and a flag signal, and a rendering circuit configured to output a data signal corresponding to a current line in response to a next intermediate data signal corresponding to a next line, to output a current intermediate data signal corresponding to the current line from the memory, and to output a previous flag signal corresponding to a previous line from the memory.
Abstract:
A display apparatus includes gate lines extending in a first direction, data lines extending in a second direction crossing the first direction, first color pixels, and second color pixels. A first color pixel arranged in an f-th column between an f-th data line and an (f+1)th data line is connected to one of the f-th data line and the (f+1)th data line. A first color pixel arranged in a g-th column between a g-th data line and a (g+1)th data line is connected to one of a (g−1)th data line and a (g+2)th data line. First color pixels in a first color pixel diagonal group receive data voltages having a same polarity.Second color pixels in a second color pixel diagonal group receive data voltages having a same polarity.