公开(公告)号：US12300184B2

公开(公告)日：2025-05-13

申请号：US18143035

申请日：2023-05-03

Applicant: Samsung Display Co., Ltd.

Inventor： Jaesic Lee ,  Wonkyu Kwak ,  Kyunghoon Kim ,  Mincheol Lee

IPC: G09G3/3275

Abstract: Provided is a display apparatus comprising a data driving circuit configured to output data signals through a plurality of output lines, a data distribution circuit including a first switch and a second switch, wherein the first switch connects a first data line to a first output line in response to a first control signal, and the second switch connects the second data line to the first output line in response to a second control signal, and a control circuit configured to alternately output the first control signal and the second control signal during each line time of one frame.

公开(公告)号：US12106690B2

公开(公告)日：2024-10-01

申请号：US17974638

申请日：2022-10-27

Applicant: Samsung Display Co., LTD.

Inventor： Dongsun Lee ,  Wonkyu Kwak ,  Dong Eup Lee ,  Dongsoo Kim ,  Seungwoo Sung ,  Mincheol Lee

IPC: G09G3/00 ,  G09G3/3233

CPC classification number: G09G3/006 ,  G09G3/3233 ,  G09G2330/12

Abstract: A method includes applying first different voltages to pixels included in a reference pixel column and pixels included in a pad adjacent pixel column electrically connected to a second pad adjacent to a first pad connected to the reference pixel column, and applying second different voltages to the pixels included in the reference pixel column and to pixels included in a line adjacent pixel column electrically connected to a second data line adjacent to a first data line connected to the reference pixel column.

公开(公告)号：US20230368742A1

公开(公告)日：2023-11-16

申请号：US18143035

申请日：2023-05-03

Applicant: Samsung Display Co., Ltd.

Inventor： Jaesic Lee ,  Wonkyu Kwak ,  Kyunghoon Kim ,  Mincheol Lee

IPC: G09G3/3275

CPC classification number: G09G3/3275 ,  G09G2300/0452 ,  G09G2310/0272

Abstract: Provided is a display apparatus comprising a data driving circuit configured to output data signals through a plurality of output lines, a data distribution circuit including a first switch and a second switch, wherein the first switch connects a first data line to a first output line in response to a first control signal, and the second switch connects the second data line to the first output line in response to a second control signal, and a control circuit configured to alternately output the first control signal and the second control signal during each line time of one frame.