公开(公告)号：US09704449B2

公开(公告)日：2017-07-11

申请号：US14836200

申请日：2015-08-26

Applicant: Samsung Display Co., Ltd.

Inventor： Se-Hyang Kim ,  Kyung-Hoon Kim ,  KyoungHo Lim ,  Kwang-chul Jung ,  Junki Jeong

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0281

Abstract: The gate driving circuit includes an (m−1)-th stage externally receiving a first dummy signal for a first time period to control a turn-off, an m-th stage externally receiving a second dummy signal for the first time period to control the turn-off, an (m−2)-th stage receiving an m-th carry signal for a second time period from the m-th stage and externally receiving the second dummy signal for the second time period to control the turn-off, and an (m−3)-th stage receiving an (m−1)-th carry signal for the second time period from the (m−1)-th stage and externally receiving the first dummy signal for the first time period to control the turn-off, wherein the first time period is longer than the second time period.