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公开(公告)号:US20200335524A1
公开(公告)日:2020-10-22
申请号:US16832796
申请日:2020-03-27
Applicant: Samsung Display Co., Ltd.
Inventor: Dong Bum LEE , Chul Ho KIM , Yun Hwan PARK , In Jun BAE , Woo Ri SEO , Jin JEON
IPC: H01L27/12 , H01L23/552 , H01L31/14
Abstract: A display device includes: a substrate; an active layer; a first insulating layer on the active layer; a gate electrode; a second insulating layer on the first conductive layer; a second conductive layer on the second insulating layer; a third insulating layer on the second conductive layer; and a source electrode connected to the source region of the first active pattern through a contact hole passing through the first insulating layer and the second insulating layer, and a drain electrode connected to the drain region, wherein the first active pattern, the gate electrode, the source electrode and the drain electrode constitute a thin film transistor, the display device further comprising at least one light shielding pattern around the thin film transistor, wherein the light shielding pattern includes a side light shielding pattern such that the third conductive layer passes through at least the third insulating layer.
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公开(公告)号:US20230036497A1
公开(公告)日:2023-02-02
申请号:US17745179
申请日:2022-05-16
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Yong Jae KIM , Yun Hwan PARK , Woo Ri SEO , Yoon Jee SHIN
IPC: G09G3/32
Abstract: A display device includes a pixel, a scan driver supplying first to third scan signals in a first non-emission period and supplying the second scan signal in a second non-emission period, an emission driver supplying an emission control signal in the first and second non-emission periods, and a data driver supplying a data signal in the first non-emission period. The pixel includes a light-emitting element, a first transistor, a second transistor connected between the data line and a second node, a first capacitor connected between the first and second nodes, a third transistor connected between a third power line and the first node, a storage capacitor connected between the first and third nodes, a fourth transistor connected between the third node and a fourth power line, a fifth transistor connected between the first power line and the first transistor, and a sixth transistor supplying a fifth supply voltage.
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