公开(公告)号：US20250139006A1

公开(公告)日：2025-05-01

申请号：US18741764

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aditya Madhusudan DESHPANDE ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Manisha GAJBE

IPC: G06F12/0806

Abstract: In some aspects, the techniques described herein relate to a device including a storage media and a processor including a cache hierarchy including a first cache, a second cache, and a third cache, wherein the first cache and the third cache are organized in an inclusive cache hierarchy, and wherein the second cache is an exclusive cache to the inclusive cache hierarchy; and a cache directory, wherein the cache directory corresponds to the first cache, second cache, and third cache. In some aspects, the processor performs operations including searching the first cache for data, searching the second cache for the data, and searching the cache directory for the data. In some aspects, searching the cache directory includes determining that the data is located in the cache directory and determining a location of the data in the cache hierarchy based on an entry in the cache directory.

公开(公告)号：US20250117337A1

公开(公告)日：2025-04-10

申请号：US18587940

申请日：2024-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aditya Madhusudan DESHPANDE ,  Douglas JOSEPH ,  Manisha GAJBE ,  Arun RODRIGUES

IPC: G06F12/1027

Abstract: Provided are systems, methods, and apparatuses for transferring computational tasks. In one or more examples, the systems, methods, and apparatuses include a first host configured to detect a trigger to offload instruction code from the first host to a second host; identify, based on the trigger, an address translation binding for the instruction code and an address translation binding for application data associated with the instruction code; copy the address translation binding for the instruction code and the address translation binding for the application data to a memory; and transfer control of execution of the instruction code to the second host based on the copying.

公开(公告)号：US20250165658A1

公开(公告)日：2025-05-22

申请号：US18638647

申请日：2024-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nichols Anthony ROMERO ,  Robert William WISNIEWSKI ,  Aditya Madhusudan DESHPANDE ,  Manisha GAJBE ,  Arun Francis RODRIGUES ,  Matthew Douglas TURNER

IPC: G06F30/13

Abstract: Provided are systems, methods, and apparatuses for iterative guided architecture design based on self-optimizing analytical models. In one or more examples, the systems, devices, and methods include determining a figure of merit (FOM) of a reference architecture based on executing a workload on the reference architecture and measuring a hardware event associated with executing the workload. In some examples, the systems, devices, and methods include determining an analytical model based on the FOM and based on performing roofline analysis on the reference architecture. In some examples, the systems, devices, and methods include estimating performance of the workload on the target architecture based on the analytical model identifying an optimal design based on validating the analytical model on a plurality of architectures executing the workload.