公开(公告)号：US20220066829A1

公开(公告)日：2022-03-03

申请号：US17453945

申请日：2021-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ashutosh PAVAGADA VISWESWARA ,  Pallavi THUMMALA ,  Chirag GIRDHAR ,  Alladi Ashok Kumar SENAPATI ,  Pradeep N S NELAHONNE SHIVAMURTHAPPA ,  Venkappa MALA

IPC: G06F9/50 ,  G06F9/445

Abstract: Disclosed herein is a method and an optimization unit for optimizing and/or improving efficiency of resource utilization in an embedded computing system executing Artificial Intelligence (AI) applications. The method includes: detecting, by an optimization unit comprising processing circuitry and/or executable program instructions configured in the embedded computing system, a launch of an AI application on the embedded computing system; retrieving a runtime profile corresponding to the AI application, the runtime profile indicating resource requirements for executing the AI application; and configuring a runtime environment of the embedded computing system for the AI application based on the runtime profile corresponding to the AI application.

公开(公告)号：US20240135181A1

公开(公告)日：2024-04-25

申请号：US18541972

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gokulkrishna M ,  Siva Kailash SACHITHANANDAM ,  Prasanna R ,  Rajath Elias SOANS ,  Alladi Ashok Kumar SENAPATI ,  Praveen Doreswamy NAIDU ,  Pradeep NELAHONNE SHIVAMURTHAPPA

IPC: G06N3/08 ,  G06N3/045

CPC classification number: G06N3/08 ,  G06N3/045

Abstract: A method for validating a trained artificial intelligence (AI) model on a device is provided. The method includes deploying a validation model generated by applying a plurality of anticipated configurational changes associated with the trained AI model requiring validation. Further, the method includes providing input data to each of the validation model and the trained AI model for receiving an output from each of the validation model and the trained AI model, wherein the output of the validation model is further based on one or more actual configurational deviations that occurred during training of the trained AI model since deployment of the trained AI model on the device. Furthermore, the method includes combining the output of each of the validation model and the trained AI model to validate the trained AI model.

公开(公告)号：US20230252756A1

公开(公告)日：2023-08-10

申请号：US18172774

申请日：2023-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rajath Elias SOANS ,  Pradeep NELAHONNE SHIVAMURTHAPPA ,  Kuladeep MARUPALLI ,  Alladi Ashok Kumar SENAPATI ,  Ananya PAUL

IPC: G06V10/26 ,  G06V10/25 ,  G06V10/82

CPC classification number: G06V10/267 ,  G06V10/25 ,  G06V10/82

Abstract: A method for processing an input frame for an on-device AI model is provided. The method may include obtaining an input frame. The method may include building at least one kernel independent of the scale of the input frame by passing input variables to the at least one kernel using preprocessor directives independent of the scale of the input frame. The method may include inputting the input frame to the on-device AI model including the at least one kernel independent of the scale of the input frame. The method may include processing the input frame in the on-device AI model.

公开(公告)号：US20220366217A1

公开(公告)日：2022-11-17

申请号：US17864596

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Briraj SINGH ,  Amogha UDUPA SHANKARANARAYANA GOPAL ,  Aniket DWIVEDI ,  Bharat MUDRAGADA ,  Alladi Ashok Kumar SENAPATI ,  Suhas Parlathaya KUDRAL ,  Arun ABRAHAM ,  Praveen Doreswamy NAIDU

IPC: G06N3/04

Abstract: Embodiments herein provide a method and system for network and hardware aware computing layout selection for efficient Deep Neural Network (DNN) Inference. The method comprises: receiving, by the electronic device, a DNN model to be executed, wherein the DNN model is associated with a task; dividing the DNN model into a plurality of sub-graphs, wherein each sub-graph is to be processed individually; identifying a computing unit from a plurality of computing units for execution of each sub-graph based on a complexity score; and determining a computing layout from a plurality of computing layouts for each identified computing unit, wherein the sub-graph is executed on the identified computing unit through the determined computing layout.