公开(公告)号：US20230071420A1

公开(公告)日：2023-03-09

申请号：US17874927

申请日：2022-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae In LEE ,  Byung Jin CHO ,  Jung Hoon LEE ,  Jaeduk LEE

IPC: H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, and vertical channel structures provided in vertical channel holes penetrating the stack structure. Each of the vertical channel structures may include a data storage pattern covering an inner side surface of each of the vertical channel holes, a vertical semiconductor pattern covering the data storage pattern, and a gapfill insulating pattern filling an internal space enclosed by the vertical semiconductor pattern. The vertical semiconductor pattern may have a first surface which is in contact with the gapfill insulating pattern, and a second surface which is in contact with the data storage pattern. A germanium concentration in the vertical semiconductor pattern may decrease in a direction from the first surface toward the second surface.